| A | B |
|---|
| PROM | Programmable Read Only Memory |
| EPROM | Erasable Programmable ROM |
| EEPROM | Electonically Erasable Programmable ROM |
| SRAM | Static Random Access Memory |
| SDRAM | Synchronous Dynamic Random Access Memory |
| DRAM | Dynamic Random Access Memory |
| Memory Access Time | Time required to produce the required data from the start of the access until valid data is available for use. |
| Memory Latency | Time taken for the first access to memory. |
| Burst Mode Access | Bursting is a rapid data-transfer technique that automatically generates a block of data every time the processor rquests an address. |
| Asynchronous | Not synchronised to the system clock. |
| FPM | Fast Page Mode. |
| Fast Page Mode | A timing option that permits several bits of data in a single row on DRAM to be accessed at an accelerated rate. |
| EDO | Extended Data Out |
| EDO DRAM | RAM that doesn't demand that the column be deactivated and the out put buffer turned off before the next data transfer takes place. |
| BEDO DRAM | Special features to increase data transfer. Faster than EDO DRAM. |
| Synchronous | SDRAM supplies the bits as fast as the CPU can take them, using a clock to synchronise the timing of the memory chip to the CPU's clock. |
| Parity | For every 8 bits of data, and extra bit called the parity bit is generated and stored for checking the validity of the data. |
| ECC | Error correction code. |
| Error Correction Code (ECC) | ECC memory uses addition bits - 5 bits to protect 8-bit words. It is capapble of detecting 1-bit errors. |
| DIP | Dual Inline Package |
| SIMM | Single Inline Memory Module |
| DIMM | Dual Inline Memory Module |
| Linear Addressing | The full address (memory location) |
| Segmented addressing | Seperate register for segment information and other for the offset. |
| Address Bus | Determines the memory space accessible |
| Internal L1 Cache | L1 Cache is built into the CPU die |
| Write through Cache | The CPU writes information to cahce, and is automatically written to memory at the same time. |
| Write Back Cache | Is when the CPU write data is also cahced. |
| RISC | Reduced Instruction Set Computer |
| CISC | Complex Instruction Set Computer |
| MMX | Multimedia Extensions |
| SIMD | Single Instruction Multiple Data |
| SSE | Streaming SIMD Extensions |
| Dynamic Execution | Multiple branch prediction, which uses dataflow analysis to look for out-of-order instruction execution. |
| Specualtive Execution | Executes instructions ahead of actual program counter. |
| Dual Independant Bus Architechture | Includes the System Bus or processor to main memory bus and the backside bus in the processor used for L2 Cache (at processor speed). |
| PGA | Pin Grid array |
| ZIF | Zero Insertion Force |
| LIF | Low Insertion Force |
| What is the size of the Data bus of the INtel 8088 porcessor | 8 bit |
| What is the AT compatible operating mode of the 486 processor? | Virtual Real Mode |
| What is the size of the data bus of the Pentium Processor | 64 bit |
| What does Dual Inline(independant) Bus mean? | It meas there is a seperate independant bus connecting the CPU and the Cache |
| What is the data bus size for the AGP slot? | 32 bit |
| What is another name for the Refresh Rate with regard to a CRT monitor | Vertical Scan Rate |
| What Charateristic does a CPU have if it is super scaler? | Dual pipeline, parallel processing (more than one instruction per cycle) |
| What are the key features of a Superscaler CPU? | Twin Data Pipelines, can execute 2 instructions at a time. |
| List anti static procedures: | Use correct anti-static equipment, wrist strap, anti-static mat,... hold components by the end plate, never touch connectors or circuits. |
| How many pins are there on a SIMM capable of storing 32bits? | 72 Pins |
