| A | B |
|---|
| Power Supply | The Component that supplies the power to the computer and converts AC to DC |
| Keyed Components | A component whose connector is designed such that connecting cables can only be attached in one way |
| UPS | an uninteruptable power supply is a device intended to save computer compontnes from damage due to power problems such as failuers, spikes, and sags |
| Standby UPS | SUPS are UPSs that supplies power from a battery when poerw problems are detected |
| Online UPS | A UPS that supplies power from a battery at all time. the battery is recharged from the regular electrical supply |
| Line Conditioner | A device that reduces noise and some power problems, mainly implemented because of it's ability to reduce electrico magnetic interference (EMI) and Radio Frequency Interference (RFI) |
| BIOS | Basic Input/Output System. Low-Level software that acts as the interface between the hardware and the Operating System in a computer |
| POST | Power On Self Test. A series of Built in diagnositcs that are preformed when the computer is first, they make POST codes that indicate test results |
| Plug and Play | Method to have the OS automatically configure adapter settings, aka PnP |
| CMOS | Complimentary Metal Oxide Semiconductor, The most widely used type of intergtated circut for digital processors and memmories, virtually everything is configured through CMOS today. |
| CPU | Central Prosessing Unit. the main chip on the system board the CPU preforms software instructions and mathmatical and logical equations |
| ZIF socket | Zero Insertion Source is a type of processor socket that uses a lever to tighten or lossen the pin connections between the processor chip ant the socket |
| CISC | Complex Instruction Set Computer. THese are processes that don't require instructions to be of a fixed legnth, and that allow for more complicated functions to be excuted in one instructions |
| RISC | Reduced Instruction Set Computer. These are Processors that require instructions to be of a fixed legnth, making their instructions simpler, and fewer, than CISC, but more instructions a required to carry out a single function. |
| Real Mode | an operational state in intel CPU chips (starting w/ 286) in which the comp functions like the first Intel CPU chip (8086/8088) which is limited to accessing 1mb of memory. DOS applications run in real mode, unless they have been enhanced with a DOS extender that allows more memmory usage |
| coventional memory | In a PC the First 604 k of memory |
| Protected Mode | in PCs, starting w/ 286, an operational state that allows the comp to address all memory |
| Virtual Machine | The ability of a CPU to preform as multiple 8086 CPUs, Under direction of a control program, each virtual machine runs as a stand-alone 8086 running it's own OS and applications |
| Math Coprosessor | A Mathmatical circut that preforms high-speed floating point opperations, it is mostly built into the CPU chip, in older systems the math coprossesor was optional and seprate |
| Cache | Dedicated high-speed Memory for Storing recently used instruction and data |
| Dual-Voltage | Design that enables use of a higher external voltage (also called I/O voltage), and a lower internal (also called core) voltage for processors. also called split-rail |
| Superscaler | Technology that enables the CPU to execute two instructions simultaneously, using the U and V pipelines |
| Superpipelining | The Ability of the CPU chip to overlap the execution steps (Fetch, Decode, Execute, and Write) of fuor instructions. |
| Speculative Execution | The process of the CPU trying to guess which instruction will be used next, and executing one or more instructions as a result of the guess |
| branch prediction | the prosess of the CPU trying to anticipate which code will be used next |
| register renaming | technology that uses multiple sets of registers in the processor to provide multiple execution paths |
| out-of-order completion | Technology that enables superscaler processors to re-assemble the results of instructions |
| dib | Dual Independant Bus is the arctitecture |
| MMX | a set of additional instructions to support multimedia functions and beyond |
| SIMD | Single Instructions Multiple Data is a processing technique that allows a single instruction to work on multiple pieces of data |
| EPIC | Explicitly Parallel Instruction Computing |
| MIPS | Millions of Instructions Per Second, execution speed of a comp |
| Heat Sink | A device attached to a processor that addresses the problem of overhating |
| DIP | Dual in line packages are |
| PGA | pin grid array is a tpe of CPU packaging design on which pins are distributed evenly |
| SPGA | Stagared Pin Grid Array. this CPU packaging design staggers pins so that more pins will fit on the same amount of surface |
| SECC | Single Edge Cntact Cartridge, a type of CPU packaging that refers to the design where the processor is located |
| Overdrive Chip | Chip that Enables you to upgrade a comps preformace simply by replacing the original porcessor with a new processor on the old |
| bus | a set of physical and logical interconnections between te computer and add-on boards |
| datapath | the number of bits wide or the number of channels in the bus |
| CMOS | Complimentary |
