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| AND Gate | Digital circuit that implements the AND operation. The output of this circuit is HIGH only if all of its inputs are HIGH. |
| Boolean Expression | An algebraic expression made up of Boolean variables and operators, such as AND (-), OR (+), or NOT (-). Also referred to as Boolean function or a logic function. |
| Clocked D Flip-Flop | Type of flip-flop in which the D (data) input is the synchronous input. |
| Combinational Logic | Digital circuitry in which an output is derived from the combination of inputs, independent of the order in which they are applied. |
| Datasheet | A printed specification giving details of the pin configuration, electrical properties, and mechanical profile of an electronic device. |
| Digital Waveform | A series of logic 1s and 0s plotted as a function of time. |
| Dual In-Line Package (DIP) | One style of integrated circuit package which has two rows of lead. |
| Flip-Flop | A sequential circuit based on a latch whose output changes when its CLOCK input receives a pulse. |
| Frequency | The number of cycles per unit time of a periodic waveform. |
| Integrated Circuit (IC) | An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package. |
| Inverter | Also called a NOT gate or an inverting buffer. A logic gate that changes its input logic level to the opposite state. |
| Large Scale Integration (LSI) | An IC that contains circuitry equivalent to 100 gates or more. |
| Logic Diagram | A diagram, similar to a schematic, showing the connection of logic gates. |
| Logic Gate | An electronic circuit that performs a Boolean algebraic function. |
| Medium Scale Integration (MSI) | An IC that contains circuitry equivalent to more than 11 and less than 100 gates. |
| NOT Circuit | Also called an INVERTER gate or an inverting buffer. A logic gate that changes its input logic level to the opposite state. |
| OR Gate | Digital circuit that implements the OR operation. The output of this circuit is HIGH (logic level 1) if any or all of its inputs are HIGH. |
| Period | The amount of time required for one complete cycle of a periodic event or waveform. |
| Plastic Leaded Chip Carrier (PLCC) | Surface-mount integrated circuit package with leads that bend back under the package. |
| Propagation Delays (tPLH/tPHL) | Delay from the time a signal is applied to the time when the output makes its change. |
| Schematic Entry | A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD. |
| Schottky TTL | TTL subfamily that uses the basic TTL standard circuit except that it uses a Schottky barrier code (SBD) connected between the base and the collector of each transistor for faster switching. |
| Sequential Logic | Digital circuitry in which the output state of the circuit depends not only on the states of the inputs, but also on the sequence in which they reached their present states. |
| Simulation | Testing design function by specifying a set of inputs and observing the resultant outputs. Simulation is generally shown as a series of input and output waveforms. |
| Small-Scale Integration (SSI) | An integrated circuit having 12 or fewer gates in one package. |
| Small Outline Integrated Circuit (SOIC) | Dual-inline style surface-mount IC package. |
| Transistor-Transistor (TTL) | A family of digital logic devices whose basic element is the bipolar junction transistor. |
| Truth Table | A list of all possible input values to a digital circuit, listed in ascending binary order, and the output response for each input combination. |
| 555 Timer | TTL-compatible IC that can be wired to operate in several different modes, such as a one-shot and an astable multivibrator. |
