| A | B |
|---|
| bus | 32 bit printed circuits to transmit electronic signals |
| bus speed | speed at which data is moving |
| chip set | controls memory cache, external buses. and some peripherals |
| dimm | dual in line memory module 64 bit path |
| dram | dynamic ram |
| edo | extended standard industry architecture |
| eisa bus | extended industry standard architecture |
| external cache | level 2 |
| internal cache | level 1 |
| edo | extended data output |
| megahertz | one million clock cycles per second |
| Interrupt handler | a program that services a device when the CPU handles an IRQ request for service. Another name for a device driver. |
| multiplier | the factor by which the bus speed is multiplied to get the CPU clock speed. |
| heat sink | mounteed on CRU to dissipate heat. |
| plug and play | bios automatically configures new hardware |
| pci | a bus that runs up to 33mhz, witha 32 bit path. |
| refresh | the process of periodically rewriting data on dynamic RAM |
| wait state | a clock tick in which nothing happens |
| sram | expensive chips that retain information as long as opwer is on |
| usb | developed by Intel to be used by modems, joysticks,mice, scanners, etc... |
| polling | CPU checking for status of connected devices such as printers |
| stack | a place in memory where information, such as addresses of pending tasks for the CPU, is kept |
| parity | an error checking scheme inwhich a ninth bit is added |
