| A | B |
|---|
| 8086 | CPU CHIP THAT DEFINED THE BASE ARCHITECTURE OF THE X86 FAMILY |
| 8088 | FIRST-GENERATION PCs(XT CLASS) USED 8 BIT DATA BUS INSTEAD OF 16 |
| 80286 | x86-FAMILY 16-BIT MICROPROCESSOR 6 & 8 MHz, SCALED UP TO 20 MHz |
| 80386 | MICROPROCESSOR USED AS CPU OF PERSONAL COMPUTERS. PROCESSOR CODE-NAMED "P3" |
| 80486 | RANGE OF INTEL CISC MICROPORCESSORS, PART OF X86 FAMILY, HAS ON-CHIP UNIFIED INSTRUCTION & DATA CACHE, FPU |
| "P" RATING | DESIGNED TO PROVIDE EASY-TO-UNDERSTAND METHOD FOR RATING PERFORMANCE |
| ADDRESS BUS WIDTH | CONTROLS THE ADDRESSABILITY OF THE SYSTEM MEMORY |
| AMD | MANUFACTURER OF CHIPS FOR PERSON COMPUTERS INCLUDING ATHLON AND DURONS |
| CACHE | FAST STORAGE AREA NEAR OR IN THE CPU |
| CELERON | FAMILY OF LOWER-COST PENTIUM CHIPS FROM INTEL |
| DX | TECHNOLOGY THAT HAS ENHANCEMENTS OVER SX VERSION OF SAME PROCESSOR |
| DX2 | 486 THAT TRIPLES INTERNAL SPEEDS BUT DOES NOT CHANGE ANY EXTERNAL CONNECTIONS |
| FCPGA | SIMILAR TO PPGA, EXCEPT THAT THE SILICON CORE IS FACING UP & HEAT SLUG EXPOSED |
| FPU | SAME AS MATH COPROCESSOR |
| L1 CACHE | MEMORY CACHE BUILT INTO CPU CHIP - MEMORY CLOSEST TO CPU |
| L2 CACHE | MEMORY CACHE THAT IS EXTERNAL TO CPU CHIP |
| L3 CACHE | EXTRA CACHE BUILT INTO THE MOTHERBOARD BETWEEN CPU & MAIN MEMORY |
| MMX | SET OF 57 ADDITIONAL INSTRUCTIONS BUILT INTO INTEL CPU CHIPS -USED FOR FASTER AUDIO, VIDEO, GRAPHICS AND MODEM OPERATIONS |
| MULTITHREADING | PROCESS WHERE SEVERAL PARTS OF A SINGLE PROGRAM ARE EXECUTED AT THE SAME TIME |
| OVERCLOCKING | PRATICE OF MAKING A CPU RUN AT A HIGHER CLOCK SPEED |
| OVERDRIVE | A USER-INSTALLABLE MICROPROCESSOR FROM INTEL FOR 486 TO MAKE PROCESSOR FASTER |
| PGA | UNDERSIDE OF THE PACKAGE LINES UP IN PERFECT ROWS & COLUMNS |
| PIPELINE | PROCESSING DATA IN SERIES SO THE OUTPUT OF 1 STAGE BECOMES THE INPUT OF THE NEXT STAGE |
| PPGA | SAME AS PGA ONLY IN A PLASTIC CASE |
| REGISTER | PART OF CPU USED AS STORAGE LOCATION |
| RISC | COMPUTER ARCHITECTURE THAT REDUCES CHIP COMPLEXITY BY USING SIMPLER INSTRUCTIONS (REDUCED INSTRUCTION SET COMPUTER) |
| SECC | CHIP MODULE FROM INTEL THAT CONTAINS CPU & L2 CACHE CHIPS & PLUSGS INTO SLOT 1(SINGLE EDGE CONTACT CARTRIDGE |
| SECCS | SLOT MADE FOR PII & PIII XEON PROCESSORS; PLUGS INTO SLOT 1 |
| SX | VERSION OF INTEL PROCESSORS THAT RAN AT SLOWER SPEEDS, USUALLY ADRESSED LESS MEMORY & SUPPORTED SMALLER BUSES |
| WRITE BUFFERS | AREA USED TO HOLD RESULTS OF A PROCESSED OPERATION UNTIL THEY CAN BE WRITTEN BACK TO REGISTERS OR MEMORY |
| X86 | STANDARD THAT REPRESENTS ALL INTEL OR OTHER PROCESSORS THAT ARE PATTERNED AFTER THE 8086 & FURTER PROCESSORS |
| ZIF | TYPE OF SOCKET THAT DOES NOT REQUIRE FORCE TO INSTALL A PROCESSOR. SMALL LEVER THAT OCKS PROCESSOR INTO PLACE ONE INSTALLED (ZERO INSERTION FORCE) |
